Note: Ensure the user guide version matches your binary installation. Attempting to use Milkyway database commands in an NDM environment will result in execution syntax errors. 3. Key Stages Detailed in the ICC User Guide Flow
Synopsys provides several specialized guides depending on your stage in the design flow. You can find detailed versions like the IC Compiler™ II Multivoltage User Guide to manage complex power domains or the IC Compiler™ II Design Planning User Guide for early-stage floorplanning and hierarchy management. Key Manuals for Your Flow
# Example setup commands create_mw_lib my_design_lib -technology tech_file.tf -mw_reference_library ref_lib open_mw_lib my_design_lib read_verilog my_netlist.v current_design my_top_level link read_sdc my_constraints.sdc Use code with caution. Step 2: Floorplanning
Balancing clock skew and minimizing insertion delay. synopsys icc user guide pdf
Coarse placement, high-fanout net synthesis (HFNS), and legalization.
Fixing hold time violations introduced by the new clock tree. 5. Routing
Ensure you have the following prerequisites in your directory structure: Note: Ensure the user guide version matches your
Floorplanning defines the physical boundaries of your chip, block, or macro. The guide details how to:
Before physical layout begins, logical libraries, physical constraints, and gate netlists must be mapped.
Then treat it like a dictionary, not a textbook. Your future self (and your schedule) will thank you. Key Stages Detailed in the ICC User Guide
Assigns nets to global routing bins based on resource availability. Track Assignment: Maps nets to specific layout tracks.
The of your design (Floorplanning, Placement, CTS, or Routing)
Official, verified copies of the IC Compiler Implementation User Guide , IC Compiler II Design User Guide , and Synopsys Timing Constraints (SDC) Quick Reference must be downloaded directly via your corporate SolvNetPlus account.
Defining the shape (width vs. height) of the core.